1. Field of the Invention
The present invention relates to a semiconductor memory device having a multi-layer structure in which cross-point type memory cells are stacked.
2. Description of the Related Art
There has conventionally been known a flash memory, as an electrically rewritable nonvolatile memory, which includes a memory cell array of NAND-connected or NOR-connected memory cells having a floating gate structure. A ferroelectric memory is also known as a nonvolatile fast random access memory.
On the other hand, technologies of pattering memory cells much finer include a resistance variable memory, which uses a variable resistor in a memory cell as proposed. Known examples of the variable resistor include a phase change memory element that varies the resistance in accordance with the variation in crystal/amorphous states of a chalcogenide compound; an MRAM element that uses a variation in resistance due to the tunnel magneto-resistance effect; a polymer ferroelectric RAM (PFRAM) memory element including resistors formed of a conductive polymer; and a ReRAM element that causes a variation in resistance on electrical pulse application (Patent Document 1: Japanese Patent Application Laid-Open No. 2006-344349, paragraph 0021).
The resistance variable memory may configure a memory cell with a serial circuit of a Schottky diode and a resistance variable element in place of the transistor. Accordingly, it can be stacked easily and three-dimensionally structured to achieve much higher integration advantageously (Patent Document 2: Japanese Patent Application Laid-Open No. 2005-522045).
However, in the above-mentioned memory having the multi-layer structure, the length of the wiring at the contact portion in the stacking direction increases, so that the resistance value at the contact portion increases with the microfabrication of the wiring pitch. Therefore, there arises a problem of increasing an IR drop.